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Low-Cost Packaging of 300 GHz Integrated Circuits With an On-Chip Patch Antenna

Placing a 300 GHz on-chip patch antenna in a low-cost quad-flat no-lead (QFN) package using materials based on silica microparticles dispersed in an epoxy matrix can improve the antenna performance. Full-wave simulations of a rectangular patch antenna, compliant with the metal stack and design rules...

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Bibliographic Details
Published in:IEEE antennas and wireless propagation letters 2019-11, Vol.18 (11), p.2444-2448
Main Authors: Bakshi, Harshpreet S., Byreddy, Pranith R., O, Kenneth. K., Blanchard, A., Lee, Mark, Tuncer, Enis, Choi, Wooyeol
Format: Article
Language:English
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Summary:Placing a 300 GHz on-chip patch antenna in a low-cost quad-flat no-lead (QFN) package using materials based on silica microparticles dispersed in an epoxy matrix can improve the antenna performance. Full-wave simulations of a rectangular patch antenna, compliant with the metal stack and design rules of a 65 nm complementary metal-oxide-semiconductor (CMOS) process, show 13% radiation efficiency, 1 dB peak antenna gain, and 7 GHz -10 dB |S11| bandwidth increases when the thickness of packaging material over the antenna is ~λ/3. When placed in a QFN package, 276 GHz CMOS signal generators with the same on-chip antenna show the effective isotropic radiated power ~6 dB higher than that of unpackaged. This improvement is partly attributed to the antenna performance enhancement and demonstrates that it is possible to package 300 GHz integrated circuits with an on-chip patch antenna using a low-cost technique.
ISSN:1536-1225
1548-5757
DOI:10.1109/LAWP.2019.2943371