Modified dynamic current mode logic based LFSR for low power applications

• Published in: Microprocessors and microsystems 2020-02, Vol.72, p.102945, Article 102945
• Main Authors: Babu, A Suresh, Anand, B
• Format: Article
• Language: English
• Subjects: Circuits; Clock divider; CMOS; Exclusive-OR; Fibonacci; Hardware; Leakage; Linear feedback shift registers; Linear functions; Logic; Power consumption; Power management; Pseudo-random sequence; Pseudorandom; Random numbers; Sequences; System effectiveness; Test patterns; White noise
• ISSN: 0141-9331; 1872-9436
• DOI: 10.1016/j.micpro.2019.102945

Shift Register, which is a cascade of flip flops shares the same clock and the outputs are connected to the data input of the next one in the chain. Linear-feedback shift register or shortly LFSR is one such shift register whose input is a linear function of its previous state. Exclusive-OR (XOR) is the most commonly used linear function. LFSR's help in generating pseudo-random numbers, fast digital counters, pseudo-noise sequences and whitening sequences. LFSR's can be realised both using hardware and software. When it comes to hardware implementation, MOS current mode logic (MCML) method can be used for designing the LFSR. There are lots of drawbacks with the traditional MCML method including the static power dissipation, more power consumption at low frequencies as compared with CMOS circuits, inappropriate for large systems involving power-down modes and it's not a cost effective solution either. To overcome these issues and to achieve the high speed characteristics of MCML, we present the modified dynamic current mode logic and is a good solution for battery powered systems and portable solutions. Our simulation results also confirm the same where a 16 bit adder circuit fabricated using CMOS technology has only a delay of 1.22 ns and dissipates 19.0 mW at 400 MHz.