Reversible hysteresis inversion in MoS2 field effect transistors

• Published in: NPJ 2D materials and applications 2017-10, Vol.1 (1), Article 34
• Main Authors: Kaushik, Naveen, Mackenzie, David M. A., Thakar, Kartikey, Goyal, Natasha, Mukherjee, Bablu, Boggild, Peter, Petersen, Dirch Hjorth, Lodha, Saurabh
• Format: Article
• Language: English
• Subjects: 639/301/1005/1007; 639/925/357/1018; Air gaps; Chemistry and Materials Science; Computer simulation; Contact resistance; Defects; Field effect transistors; Hysteresis; Materials Science; Molybdenum disulfide; Multilayers; Nanotechnology; Pulsed current; Room temperature; Semiconductor devices; Silicon dioxide; Substrates; Surfaces and Interfaces; Temperature; Temperature dependence; Temperature sensors; Thin Films; Threshold voltage; Transistors; Trapping
• ISSN: 2397-7132; 2397-7132
• DOI: 10.1038/s41699-017-0038-y

The origin of threshold voltage instability with gate voltage in MoS 2 transistors is poorly understood but critical for device reliability and performance. Reversibility of the temperature dependence of hysteresis and its inversion with temperature in MoS 2 transistors has not been demonstrated. In this work, we delineate two independent mechanisms responsible for thermally assisted hysteresis inversion in gate transfer characteristics of contact resistance-independent multilayer MoS 2 transistors. Variable temperature hysteresis measurements were performed on gated four-terminal van der Pauw and two-terminal devices of MoS 2 on SiO 2 . Additional hysteresis measurements on suspended (~100 nm air gap between MoS 2 and SiO 2 ) transistors and under different ambient conditions (vacuum/nitrogen) were used to further isolate the mechanisms. Clockwise hysteresis at room temperature (300 K) that decreases with increasing temperature is shown to result from intrinsic defects/traps in MoS 2 . At higher temperatures a second, independent mechanism of charge trapping and de-trapping between the oxide and p + Si gate leads to hysteresis collapse at ~350 K and anti-clockwise hysteresis (inversion) for temperatures >350 K. The intrinsic-oxide trap model has been corroborated through device simulations. Further, pulsed current–voltage ( I – V ) measurements were carried out to extract the trap time constants at different temperatures. Non-volatile memory and temperature sensor applications exploiting temperature dependent hysteresis inversion and its reversibility in MoS 2 transistors have also been demonstrated. MoS 2 devices: variable temperature measurements unveil reversible hysteresis mechanisms Defects and traps in MoS 2 van der Pauw devices give rise to a hysteresis inversion mechanism which is reversible with temperature. A team led by Saurabh Lodha at the Indian Institute of Technology Bombay performed variable temperature hysteresis measurements on four- and two-terminal MoS 2 devices, both suspended and supported on a SiO 2 substrate. The onset of a clockwise hysteresis at room temperature was attributed to intrinsic MoS 2 defects, whereas an additional mechanism resulting in an anticlockwise hysteresis was observed at higher temperature, and attributed to extrinsic charge trapping and de-trapping between the oxide and the silicon gate. By leveraging the temperature dependence of the hysteresis in MoS 2 , the authors developed a non-volatile memory and a te