Electrothermal Transport Induced Material Re Configuration and Performance Degradation of CVD Grown Monolayer MoS2 Transistors

We report, for CVD-grown monolayer MoS2, the very first results on temporal degradation of material and device performance under electrical stress. Both low and high field regimes of operation are explored at different temperatures, gate bias and stress cycles. During low field operation, current is...

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Bibliographic Details
Published in:arXiv.org 2020-06
Main Authors: Ansh, Kumar, Jeevesh, Sheoran, Gaurav, Shrivastava, Mayank
Format: Article
Language:English
Subjects:
Amorphization
Circuits
Configuration management
Low resistance
Low temperature
Molybdenum disulfide
Monolayers
Performance degradation
Photoluminescence
Room temperature
Semiconductor devices
Stress cycles
Temperature
Threshold voltage
Time constant
Transistors
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Summary:We report, for CVD-grown monolayer MoS2, the very first results on temporal degradation of material and device performance under electrical stress. Both low and high field regimes of operation are explored at different temperatures, gate bias and stress cycles. During low field operation, current is found to saturate after hundreds of seconds of operation with the current decay time constant being a function of temperature and stress cycle. Current saturation after several seconds during low field operation occurs when a thermal equilibrium is established. However, high field operation, especially at low temperature, leads to impact ionization assisted material and device degradation. It is found that high field operation at low temperature results in amorphization of the channel and is verified by device and Kelvin Probe Force Microscopy (KPFM) analyses. In general, a prolonged room temperature operation of CVD-grown MoS2 transistors lead to degraded gate control, higher OFF state current and negative shift in threshold voltage (VT). This is further verified, through micro-Raman and Photoluminescence spectroscopy, which suggest that a steady state DC electrical stress leads to the formation of localized low resistance regions in the channel and a subsequent loss of transistor characteristics. Our findings unveil unique mechanism by which CVD MoS2 undergoes material degradation under electrical stress and subsequent breakdown of transistor behavior. Such an understanding of material and device reliability helps in determining the safe operating regime from device as well as circuit perspective.
ISSN:2331-8422