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Design and Analysis of High-Voltage Blocking in Drain-Source Synchronous Rectifier Controllers for kV Operation
Traditionally, standalone closed-loop drain-source sensed synchronous rectification (SR) implementation has been limited by the voltage limits of commercial IC controllers. Commercially available SR controllers have low maximum voltage limits, necessitating a high-voltage blocking mechanism for use...
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Published in: | IEEE journal of emerging and selected topics in power electronics 2020-12, Vol.8 (4), p.4406-4415 |
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Main Authors: | , , , |
Format: | Article |
Language: | English |
Subjects: | |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
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Summary: | Traditionally, standalone closed-loop drain-source sensed synchronous rectification (SR) implementation has been limited by the voltage limits of commercial IC controllers. Commercially available SR controllers have low maximum voltage limits, necessitating a high-voltage blocking mechanism for use in higher voltage rectifiers. Therefore, in this article, a board-level blocking method to protect drain-source voltage sensed SR controllers from high voltage and currents at the board level is presented. This method allows for the high-voltage operation of drain-source SR controllers. This method is self-biasing and allows for SR controller operation far beyond the datasheet voltage limits (kV+). The mechanisms of operation are analyzed, and design criteria created for selecting an optimal clamp is proposed. The proposed solution is simple and low in cost and component count, making closed-loop, cyclically adaptive SR a practical solution for high-voltage rectifiers. The blocking circuit is presented, analyzed, and tested for use with commercially available drain-source SR controller integrated circuits (ICs). Hardware SR testing is completed on two LLC-DCX (dc-transformer) modules with 300 V, and over 1-kV output voltages to demonstrate the voltage blocking capabilities. |
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ISSN: | 2168-6777 2168-6785 |
DOI: | 10.1109/JESTPE.2019.2951631 |