Generation of complex impedance for complex filter design using fully balanced current conveyors

• Published in: Analog integrated circuits and signal processing 2020-11, Vol.105 (2), p.203-214
• Main Authors: Veerendranath, P. S., Sharma, Vivek, Vasantha, M. H., Nithin Kumar, Y. B.
• Format: Article
• Language: English
• Subjects: Circuits; Circuits and Systems; CMOS; Current conveyors; Electrical Engineering; Engineering; Figure of merit; Filter design (mathematics); Group delay; Impedance; Layouts; Noise levels; Power consumption; Signal,Image and Speech Processing; Transformations
• ISSN: 0925-1030; 1573-1979
• DOI: 10.1007/s10470-020-01618-9

In this paper a complex filter is presented where the shift in the frequency is obtained using a linear frequency transformation. The linear frequency transformation in the proposed design is implemented using a complex impedance. A complex impedance is also proposed in this paper using a Fully Balanced Second Generation Current Conveyor (FBCCII). The FBCCII design used in this paper consumes 84 μ W of power and has an open loop gain of 47.83 dB with 62 . 9 ∘ of phase margin at 39.8 MHz unity gain bandwidth. A low power 3rd order complex filter is designed by linear frequency transformation at 40 MHz center frequency. The proposed complex filter achieves a bandwidth of 9 MHz with an image rejection ratio of 45 dB. The design consumes 1.5 mW of power and has a group delay of 12.5 ns. The figure of merit of the proposed filter is 0.007 fJ with a SFDR of 63.9 dB. The output noise of the design at 40 MHz center frequency is 45.86 nV / Hz and integrated Input Referred noise is 600 μ V . The design is simulated using a 180 nm CMOS technology with a supply voltage of ± 0.5 V . The circuit’s efficacy is verified and supported by PVT and post layout simulations. The area of the layout of the proposed design is 0.624 mm 2 (i.e. 260 μ m × 240 μ m ).