Performance optimization of a nanotube core–shell semi-junctionless p+p+n heterojunction tunnel field effect transistor

In this paper, the electrical characteristics of a heterojunction nanotube semi-junctionless tunnel field effect transistor (NSJTFET) with germanium in the source and GaAs in the drain channel regions are thoroughly investigated. The proposed n-channel NSJTFET is a p + p + n structure, employing int...

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Bibliographic Details
Published in:Indian journal of physics 2021-06, Vol.95 (6), p.1091-1099
Main Author: Ahangari, Zahra
Format: Article
Language:English
Subjects:
Astrophysics and Astroparticles
Design parameters
Field effect transistors
Germanium
Heterojunctions
Mathematical analysis
Nanotubes
Nanowires
Optimization
Original Paper
Parameter sensitivity
Physics
Physics and Astronomy
Semiconductor devices
Sensitivity analysis
Threshold voltage
Transistors
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Summary:In this paper, the electrical characteristics of a heterojunction nanotube semi-junctionless tunnel field effect transistor (NSJTFET) with germanium in the source and GaAs in the drain channel regions are thoroughly investigated. The proposed n-channel NSJTFET is a p + p + n structure, employing internal core gate and external shell gate. The device under study provides a superior gate control over the channel by amplifying the band-to-band tunneling rate. The results imply that an increased on-state drive current of nearly 100 times as compared to the conventional nanowire tunnel field effect transistor (TFET) is achieved. In addition, the steep slope NSJTFET structure exhibits subthreshold swing of approximately 7.6 mV/dec in comparison with 25 mV/dec for the conventional TFET. Sensitivity analysis of main electrical parameters demonstrates that source-channel doping concentration and metal gate workfunction are critical design parameters that may affect the device performance. Moreover, a framework of core–shell gate workfunction engineering is utilized via calculating 2D variation matrix of the on-state current, threshold voltage and off-state current for optimizing the device performance.
ISSN:0973-1458
0974-9845
DOI:10.1007/s12648-020-01776-6