Improving Thermal Stability for Ge p-MOSFET of HfO2-Based Gate Stack With Ti-Doped Into Interfacial Layer by In-Situ Plasma-Enhanced Atomic Layer Deposition

• Published in: IEEE electron device letters 2021-08, Vol.42 (8), p.1109-1111
• Main Authors: Li, Hui-Hsuan, Tsai, Yi-He, Lin, Yu-Hsien, Chien, Chao-Hsin
• Format: Article
• Language: English
• Subjects: <italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">in situ; Atomic layer epitaxy; Current leakage; Doping; Germanium; germanium oxide (GeO<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">ₓ ); Hafnium oxide; hafnium oxide (HfO₂); Hole mobility; Interface stability; interfacial layer (IL); Leakage current; Logic gates; Metals; MOSFET circuits; MOSFETs; Photoelectrons; plasma-enhanced atomic layer deposition (PEALD); Spectrum analysis; Substrates; Thermal stability; titanium (Ti); X ray photoelectron spectroscopy
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2021.3087490

We successfully fabricated a Ge pMOSFET with Ti that is doped into a GeO x interfacial layer (IL) of HfO 2 -based gate stacks, doing so using in situ plasma-enhanced atomic layer deposition. X-ray photoelectron spectroscopy (XPS) spectra findings indicated that Ti-doped IL can suppress GeO x volatilization. A Ti-doped GeO x gate stack exhibited a lower interface state density of approximately 6\times 10^{{11}} eV −1 cm −2 , an equivalent oxide thickness (EOT) of 0.7 nm, and a relatively low gate leakage current of approximately 10 −4 A/cm 2 at \text{V}_{{FB}} -1\text{V} . Additionally, the Ge pMOSFET with Ti-doped GeO x reveals an improved subthreshold swing of 92 mV/decade and an effective hole mobility of 98 cm 2 / \text{V}\centerdot \text{s} . Therefore, the proposed scheme is simple for use in achieving a sub-nm EOT gate dielectric on a Ge substrate.