SAPIENS: A 64-kb RRAM-Based Non-Volatile Associative Memory for One-Shot Learning and Inference at the Edge

Learning from a few examples (one/few-shot learning) on the fly is a key challenge for on-device machine intelligence. We present the first chip-level demonstration of one-shot learning with Stanford Associative memory for Programmable, Integrated Edge iNtelligence via life-long learning and Search...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2021-12, Vol.68 (12), p.6637-6643
Main Authors: Li, Haitong, Chen, Wei-Chen, Levy, Akash, Wang, Ching-Hua, Wang, Hongjie, Chen, Po-Han, Wan, Weier, Khwa, Win-San, Chuang, Harry, Chih, Y.-D., Chang, Meng-Fan, Wong, H.-S. Philip, Raina, Priyanka
Format: Article
Language:English
Subjects:
Accuracy
Associative memory
Associative memory (AM)
Chips (memory devices)
CMOS
Cognitive tasks
Computer architecture
Feature extraction
Inference
Machine learning
memory-augmented neural networks (MANNs)
Microprocessors
Model accuracy
Neural networks
one-shot learning
Programming
Random access memory
ReRAM
Resistance
resistive random access memory (RRAM
Sensors
Voltage measurement
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Summary:Learning from a few examples (one/few-shot learning) on the fly is a key challenge for on-device machine intelligence. We present the first chip-level demonstration of one-shot learning with Stanford Associative memory for Programmable, Integrated Edge iNtelligence via life-long learning and Search (SAPIENS), a resistive random access memory (RRAM)-based non-volatile associative memory (AM) chip that serves as the backend for memory-augmented neural networks (MANNs). The 64-kb fully integrated RRAM-CMOS AM chip performs long-term feature embedding and retrieval, demonstrated on a 32-way one-shot learning task on the Omniglot dataset. Using only one example per class for 32 unseen classes during on-chip learning, SAPIENS achieves 79% measured inference accuracy on Omniglot, comparable to edge software model accuracy using five-level quantization (82%). It achieves an energy efficiency of 118 GOPS/W at 200 MHz for in-memory L1 distance computation and prediction. Multi-bank measurements on the same chip show that increasing the capacity from three banks (24 kb) to eight banks (64 kb) improves the chip accuracy from 73.5% to 79%, while minimizing the accuracy excursion due to bank-to-bank variability.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2021.3110464