Adaptive self-threshold strategy of high speed comparator-based relaxation oscillator using 0.18-μm low-power CMOS design

• Published in: Analog integrated circuits and signal processing 2022-02, Vol.110 (2), p.231-250
• Main Authors: Heidaritabar, Akbar, Adarang, Habib, Ghoreishi, Seyed Saleh, Yousefi, Reza
• Format: Article
• Language: English
• Subjects: Circuits and Systems; CMOS; Design; Electric potential; Electrical Engineering; Engineering; Frequency stability; High speed; Inverters; Noise; Power consumption; Power management; Relaxation oscillators; Signal,Image and Speech Processing; Tracking; Vibration; Voltage
• ISSN: 0925-1030; 1573-1979
• DOI: 10.1007/s10470-021-01816-z

This paper develops an integrated concept of a relaxation oscillator to increase system frequency stability and to provide anti-noise signals at a nominal frequency of 8.2 MHz using 2 swing-boosting and self-threshold tracking loop methods. In this case, based on the design of a low-power, high-speed CMOS, the proposed relaxation oscillator is provided, which develops high-speed at low power under various operating conditions. To reduce the dependence of the output voltage on the system temperature, considering self-threshold-tracking loop technique, the transient voltage signals from inverter-based comparator devices, the transient voltage signals from inverter-based comparator devices are matched to the corresponding nominal value of the reference voltage, taking into account the self-threshold tracking loop technique. In this way, the proposed self-threshold tracking loop technique compensates for the existing time delay that ensures the required power consumption of the power comparator. The proposed scheme procedure is provided for the design of the methodology considering a 0.18 μm CMOS. Regarding the design processes, an Allan noise variation of 1.56 ppm with − 109 dBc/Hz phase-based noises with an offset frequency of 100 kHz is provided, which develops a jitter period of 7.66 ps rms period through the design process. In this case, the corresponding evaluations yield 160.8 dBc/Hz with 5.6 kHz/nW power comparison efficiency, using only 46.3 μW as power consumption. In this respect, the proposed compensation scheme provides a sensitivity of 0.9%/0.1 V, which is very low compared to other conventional loops. According to the proposed relaxation oscillator scheme, there is an internal temperature of 123 ppm/°C, which is evaluated by − 20–100 °C without considering a modification procedure.