Theoretical Analysis of On-Chip Vertical Hybrid Plasmonic Nanograting

A complementary metal oxide semiconductor (CMOS) compatible photonic-plasmonic waveguide with nanoscale dimensions and better optical confinement has been proposed for the infrared (IR)–band applications. The design is based on the multi-layer hybrid plasmonic waveguide (Si–SiO 2 –Au) structure. The...

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Bibliographic Details
Published in:Plasmonics (Norwell, Mass.) Mass.), 2022-02, Vol.17 (1), p.257-263
Main Authors: Reddy, Samyuktha K., Sahu, Santosh Kumar, Khoja, Rohit, Kanu, Sumit, Singh, Mandeep
Format: Article
Language:English
Subjects:
Biochemistry
Biological and Medical Physics
Biophysics
Biotechnology
Chemistry
Chemistry and Materials Science
Circuit design
CMOS
Finite element method
Integrated circuits
Multilayers
Nanotechnology
Plasmonics
Semiconductors
Silicon dioxide
Wave propagation
Waveguides
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Summary:A complementary metal oxide semiconductor (CMOS) compatible photonic-plasmonic waveguide with nanoscale dimensions and better optical confinement has been proposed for the infrared (IR)–band applications. The design is based on the multi-layer hybrid plasmonic waveguide (Si–SiO 2 –Au) structure. The 3D-finite element method (FEM)–based numerical simulations of single slot hybrid plasmonic waveguide (HPWG) confirms 2.5 dB/cm propagation loss and 15 μm −2 confined intensity. Moreover, its application as dual-slot nanograting is studied with higher propagation length and ultra–low–dispersion near the 1550–nm wavelength. The proposed low-dispersion nanoscale grating design is suitable for future lab–on–chip nanophotonic integrated circuits.
ISSN:1557-1955
1557-1963
DOI:10.1007/s11468-021-01517-3