Total ionizing dose effect on 2-D array data transfer ICs designed and fabricated by 0.18 μm CMOS technology

• Published in: Japanese Journal of Applied Physics 2022-05, Vol.61 (SC), p.SC1081
• Main Authors: Yoda, Takashi, Ishihara, Noboru, Oshima, Yuta, Ando, Motoki, Kashiwagi, Kohei, Yoshida, Ryoichiro, Kimura, Arisa, Kuroki, Kaito, Nabeya, Shinsuke, Hirakawa, Kenji, Iwase, Masayuki, Ogasawara, Munehiro, Ito, Hiroyuki
• Format: Article
• Language: English
• Subjects: Arrays; Circuit design; circuits; CMOS; Data transfer (computers); high speed; Integrated circuits; Low power; MOSFETs; Radiation; shallow Trench Isolation (STI); Shift registers; size penalty; total Ionizing Dose (TID)
• ISSN: 0021-4922; 1347-4065
• DOI: 10.35848/1347-4065/ac48d0

Circuits for CMOS two-dimensional (2-D) array data transfer are indispensable for applications such as space and nuclear fields. Issues include being operated with higher speed, lower power, fewer size penalties, and radiation hardness. To meet these requirements, two kinds of CMOS 2-D array data transfer circuits, such as a shift register type and a memory access type, are proposed and fabricated by the standard 0.18 μ m CMOS process technology. In both types, 16 μ m pitch, 8 × 128 array data transfer operations were realized with a data rate of more than 1 Gb/s. Furthermore, we conducted 60 Co γ -ray irradiation experiments on those circuits. The current consumption ratio of the shift register type to the memory access type ranges from 150 to 200% as the dosage increases. The result indicates that the memory access type has better radiation hardness at 1 Gb/s than that of the shift register type.