High-Speed and Area-Efficient Modified Binary Divider

Division is the least commonly used of the four basic arithmetic operations because it is too difficult to utilize. The primitive use of division is an iterative subtraction. In very large-scale integration realization, the redundant representation of partial remainders and quotient digits is used i...

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Bibliographic Details
Published in:Circuits, systems, and signal processing systems, and signal processing, 2022-06, Vol.41 (6), p.3350-3371
Main Authors: Pazhani, A. Azhagu Jaisudhan, Samuel, T. S. Arun
Format: Article
Language:English
Subjects:
Adding circuits
Algorithms
Circuits and Systems
Design
Digital imaging
Digital signal processing
Dividers
Division
Electrical Engineering
Electronics and Microelectronics
Energy efficiency
Engineering
Floating point arithmetic
High speed
Image processing
Instrumentation
Multiplication & division
Power consumption
Quotients
Representations
Signal processing
Signal,Image and Speech Processing
Subtraction
Very large scale integration
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Summary:Division is the least commonly used of the four basic arithmetic operations because it is too difficult to utilize. The primitive use of division is an iterative subtraction. In very large-scale integration realization, the redundant representation of partial remainders and quotient digits is used in digit recurrence binary division. Divider modules are frequently used in digital signal processing and image processing applications. The former uses carry save representation for binary floating point division where the number of iterations is large and also occupied more area. The floating point binary division using carry save representation led to extra power consumptions for initialization and quotient digit selection. The idea is to lower the number of cycles in use while also taking up less space. Therefore, the signed-digit floating point binary division using carry increment adder has been proposed. It implies that carry increment adder has carry lookahead adder which is to minimize the propagation delay. The quotient digit selection is slightly varied to reduce the number of iterations. Result analysis shows that the area and delay are reduced compared to the floating point binary division using carry save representation. The proposed adder is suitable for high-speed applications.
ISSN:0278-081X
1531-5878
DOI:10.1007/s00034-021-01937-w