Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits

Reconfigurable field-effect transistors (RFETs) based on emerging nanotechnologies allow switching between p-type and n-type behavior at runtime upon applying different bias potentials. While prior works have focused on particular security schemes using RFETs, here we first revisit the underlying se...

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Bibliographic Details
Published in:IEEE transactions on emerging topics in computing 2022-04, Vol.10 (2), p.763-778
Main Authors: Rai, Shubham, Patnaik, Satwik, Rupani, Ansh, Knechtel, Johann, Sinanoglu, Ozgur, Kumar, Akash
Format: Article
Language:English
Subjects:
Circuit reliability
Circuits
Field effect transistors
Gates (circuits)
Hardware
hardware security
Integrated circuit modeling
Locking
Logic circuits
Logic gates
Manufacturing
Modelling
Nanotechnology
Reconfigurable FETs (RFETs)
Reconfiguration
Runtime
Security
Semiconductor devices
Short circuit currents
Silicon
silicon nanowire RFETs (SiNW RFETs)
Transistors
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Summary:Reconfigurable field-effect transistors (RFETs) based on emerging nanotechnologies allow switching between p-type and n-type behavior at runtime upon applying different bias potentials. While prior works have focused on particular security schemes using RFETs, here we first revisit the underlying security promises, and further showcase specific circuit vulnerabilities which can lead to adversarial scenarios. More specifically, first, we explore how transistor-level reconfigurability can be leveraged for logic locking and split manufacturing in the pretext of RFET-based modeling of the ITC-99 benchmarks. We find that with only 30 percent reconfigurable logic gates, we can induce a 100 percent output error rate (OER) and 31 percent Hamming distance (HD) on split manufacturing schemes. Second, arguably more disruptive, we explore how the very reconfigurability can be exploited to induce either short-circuit currents or open-circuit configurations, essentially destroying the reliability as well as electrical or functional characteristics of the chip. We apply detailed circuit evaluation and fault modeling toward this end. The novelty and severity of such disruptive scenarios lie in the fact that they can be readily realized in an actual on-field RFET-based chip, either as an adversarial or a fail-safe measure.
ISSN:2168-6750
2168-6750
DOI:10.1109/TETC.2020.3039375