Stochastic SOT Device Based SNN Architecture for On-Chip Unsupervised STDP Learning

Emerging device based spiking neural network (SNN) hardware design has been actively studied. Especially, energy and area efficient synapse crossbar has been of particular interest, but processing units for weight summations in synapse crossbar are still a main bottleneck for energy and area efficie...

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Published in:IEEE transactions on computers 2022-09, Vol.71 (9), p.2022-2035
Main Authors: Jang, Yunho, Kang, Gyuseong, Kim, Taehwan, Seo, Yeongkyo, Lee, Kyung-Jin, Park, Byong-Guk, Park, Jongsun
Format: Article
Language:English
Subjects:
Arrays
Computer architecture
Energy consumption
Hardware
Image classification
Magnetic tunneling
Magnetization
Microprocessors
Neural networks
Neurons
on-chip learning
spiking neural network
Spin-orbit torque device
stochastic spike-timing-dependent plasticity
Switches
Synapses
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Summary:Emerging device based spiking neural network (SNN) hardware design has been actively studied. Especially, energy and area efficient synapse crossbar has been of particular interest, but processing units for weight summations in synapse crossbar are still a main bottleneck for energy and area efficient hardware design. In this paper, we propose an efficient SNN architecture with stochastic spin-orbit torque (SOT) device based multi-bit synapses. First, we present SOT device based synapse array using modified gray code. The modified gray code based synapse needs only N devices to represent 2 N levels of synapse weights. Accumulative spike technique is also adopted in the proposed synapse array, to improve ADC utilization and reduce the number of neuron updates. In addition, we propose hardware friendly algorithmic techniques to improve classification accuracies as well as energy efficiencies. Non-spike depression based stochastic spike-timing-dependent plasticity is used to reduce the overlapping input representation and classification error. Early read termination is also employed to reduce energy consumption by turning off less associated neurons. The proposed SNN processor has been implemented using 65nm CMOS process, and it shows 90% classification accuracy in MNIST dataset consuming 0.78μJ/image (training) and 0.23μJ/image (inference) of energy with an area of 1.12mm 2 .
ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2021.3119180