A New Fault-Tolerant Multilevel Inverter Topology with Enhanced Reliability for PV Application

• Published in: Arabian journal for science and engineering (2011) 2022-11, Vol.47 (11), p.14841-14858
• Main Authors: Kumar, Dhananjay, Nema, Rajesh Kumar, Gupta, Sushma, Nema, Savita, Dewangan, Niraj Kumar
• Format: Article
• Language: English
• Subjects: Circuit reliability; Circuits; Control methods; Electronic devices; Engineering; Failure analysis; Failure rates; Fault tolerance; Harmonic distortion; Humanities and Social Sciences; Inverters; Markov processes; Mean time to failure; multidisciplinary; Multilevel; Photovoltaic cells; Power conditioning; Pulse duration modulation; Reliability analysis; Research Article-Electrical Engineering; Science; Switches; Topology
• ISSN: 2193-567X; 1319-8025; 2191-4281
• DOI: 10.1007/s13369-022-06992-2

Multilevel inverters (MLIs) have recently received a lot of attention in the power conditioning of photovoltaic (PV) applications. For a photovoltaic system, one of the indispensable necessities is reliability. This becomes even more vital in distant and isolated areas inaccessible for maintenance. The reliability of multilevel inverters used in photovoltaic systems is very low or vulnerable due to the high failure rate of power devices. Therefore, a new single-phase 9-level fault-tolerant topology multilevel inverter is proposed in this paper. The proposed 9-level fault-tolerant topology is able to tolerate single switch and multiple switch failures. Verification of fault-tolerance and source utilization is carried out from the experimental results and reliability evaluation is done mathematically. The process employs the analysis of failure rates of the switches and diodes of the multilevel inverter circuitry and estimation of reliability and mean time to failure (MTTF) is carried out before and after the employment of the proposed scheme using the Markov process. The sinusoidal pulse width modulation (SPWM) control method has been used as a modulation strategy to control the output voltage. The experimental results validate the effectiveness of the proposed 9-level fault-tolerant MLI topology during healthy, faulty and post-fault conditions is presented. In addition, the total harmonic distortion (THD) of the proposed 9-level fault-tolerant MLI topology during healthy and post-fault conditions is presented in the paper. Finally, the proposed 9-level fault-tolerant topology is a lesser device count compared with the existing topologies.