A Gm-Boosting Technique for Millimeter-Wave Low-Noise Amplifiers in 28-nm Triple-Well Bulk CMOS Using Floating Resistor in Body Biasing

This paper presents a simple yet effective G_{m} -boosting technique for improving gain and noise performance of millimeter-wave (mm-wave) low-noise amplifiers (LNAs) comprising triple-well transistors typically found in the modern bulk CMOS processes. The proposed technique uses a resistor that co...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2022-12, Vol.69 (12), p.5007-5017
Main Authors: Kobal, Enis, Siriburanon, Teerachot, Chen, Xi, Nguyen, Hieu Minh, Staszewski, Robert Bogdan, Zhu, Anding
Format: Article
Language:English
Subjects:
5G mobile communication
Amplification
Amplifiers
CMOS
floating resistor
Gₘ-boosting
Leakage current
Logic gates
low-noise amplifier (LNA)
Low-noise amplifiers
Millimeter wave transistors
Millimeter waves
millimeter-wave
Noise measurement
noise reduction
Resistors
Semiconductor devices
Substrates
Transconductance
Transistors
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Summary:This paper presents a simple yet effective G_{m} -boosting technique for improving gain and noise performance of millimeter-wave (mm-wave) low-noise amplifiers (LNAs) comprising triple-well transistors typically found in the modern bulk CMOS processes. The proposed technique uses a resistor that connects the p-well and deep n-well terminals of the triple-well transistor, leaving the terminals floating instead of conventionally connecting them to the ground and supply voltage. This arrangement exploits a leakage current through a diode formed between the drain/source and p-well of each transistor, thus autonomously setting its bulk potential for increased transconductance, while ensuring its robustness to the process variation. The improved isolation between the p-well and the substrate further improves the gain and noise performance. We provide a theoretical analysis of this floating resistor-based body biasing method and support it with simulation results. For experimental validation, a two-stage cascode LNA was designed and fabricated in 28-nm bulk CMOS. The measurement results show that 3.3-4dB noise figure (NF) and 19.1-16.1dB gain are achieved at 24.7-29.5GHz. To ensure a fair comparison, another identical LNA with the normally expected triple-well biasing was also fabricated. The proposed method reveals a 0.6dB improvement in minimum NF and an additional ~3.5dB gain without any significant linearity degradation.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2022.3200161