SoBS-X: Squeeze-Out Bit Sparsity for ReRAM-Crossbar-Based Neural Network Accelerator

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 2023-01, Vol.42 (1), p.204-217
• Main Authors: Liu, Fangxin, Wang, Zongwu, Chen, Yongbiao, He, Zhezhi, Yang, Tao, Liang, Xiaoyao, Jiang, Li
• Format: Article
• Language: English
• Subjects: Accelerator; Algorithms; Artificial neural networks; Co-design; Computer architecture; Hardware; Mathematical analysis; Matrix algebra; Measurement; Microprocessors; Multiplication; Network latency; neural network; Neural networks; Optimization; Pipelines; Quantization (signal); Random access memory; resistive random-access-memory (ReRAM); Routing; Sparsity; Virtual machine monitors; Workload; Workloads
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2022.3172907

Resistive random-access-memory (ReRAM) crossbar is a promising technique for deep neural network (DNN) accelerators, thanks to its in-memory and in-situ analog computing abilities for vector-matrix multiplication-and-accumulations (VMMs). However, it is challenging for crossbar architecture to exploit the sparsity in DNNs. It is inevitably complex and costly to exploit fine-grained sparsity due to the limitation of the tightly coupled crossbar structure. As a countermeasure, we develop a novel ReRAM-based DNN accelerator, named sparse-multiplication-engine (SME), based on a hardware and software co-design framework. First, we orchestrate the bit-sparse pattern to increase the density of bit-sparsity based on existing quantization methods. Such quantized weights can be nicely generated using the alternating direction method of multipliers (ADMM) optimization during the DNN fine-tuning, which can exactly enforce bit patterns in weights. Second, we propose a novel weight mapping mechanism to slice the bits of the weight across crossbars and splice the activation results in peripheral circuits. This mechanism can decouple the tightly coupled crossbar structure and cumulate the sparsity in the crossbar. Finally, a superior squeeze-out scheme empties the crossbars mapped with highly sparse nonzeros from the previous two steps. We design the SME architecture and discuss its use for other quantization methods and different ReRAM cell technologies. We further propose a workload grouping algorithm and a pipeline to achieve workload balance among crossbar-rows that concurrently execute multiply-accumulate operations to optimize the system latency. Putting all together, with the optimized model, compared with prior state-of-the-art designs, the SME shrinks the use of crossbars up to 8.7\times and 2.1\times using ResNet-50 and MobileNet-v2, respectively, and achieve average 3.1\times speed up with no or little accuracy loss on ImageNet.