Large-Scale Integrated Vector-Matrix Multiplication Processor Based on Monolayer MoS2

Led by the rise of the internet of things, the world is experiencing exponential growth of generated data. Data-driven algorithms such as signal processing and artificial neural networks are required to process and extract meaningful information from it. They are, however, seriously limited by the t...

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Bibliographic Details
Published in:arXiv.org 2023-03
Main Authors: Marega, Guilherme Migliato, Hyun Goo Ji, Wang, Zhenyu, Tripathi, Mukesh, Radenovic, Aleksandra, Kis, Andras
Format: Article
Language:English
Subjects:
Algorithms
Artificial neural networks
Computation
Computer architecture
Computer memory
Field effect transistors
Internet of Things
Mathematical analysis
Matrices (mathematics)
Microprocessors
Molybdenum disulfide
Monolayers
Neural networks
Semiconductor devices
Signal processing
Statistical analysis
Two dimensional materials
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Summary:Led by the rise of the internet of things, the world is experiencing exponential growth of generated data. Data-driven algorithms such as signal processing and artificial neural networks are required to process and extract meaningful information from it. They are, however, seriously limited by the traditional von-Neuman architecture with physical separation between processing and memory, motivating the development of in-memory computing. This emerging architecture is gaining attention by promising more energy-efficient computing on edge devices. In the past few years, two-dimensional materials have entered the field as a material platform suitable for realizing efficient memory elements for in-memory architectures. Here, we report a large-scale integrated 32x32 vector-matrix multiplier with 1024 floating-gate field-effect transistors (FGFET) that use monolayer MoS2 as the channel material. In our wafer-scale fabrication process, we achieve a high yield and low device-to-device variability, which are prerequisites for practical applications. A statistical analysis shows the potential for multilevel and analog storage with a single programming pulse, allowing our accelerator to be programmed using an efficient open-loop programming scheme. Next, we demonstrate reliable, discrete signal processing in a highly parallel manner. Our findings set the grounds for creating the next generation of in-memory processors and neural network accelerators that can take advantage of the full benefits of semiconducting van der Waals materials for non-von Neuman computing.
ISSN:2331-8422
DOI:10.48550/arxiv.2303.07183