Efficacy of Transistor Stacking on Flip-Flop SEU Performance at 22-nm FDSOI Node

• Published in: IEEE transactions on nuclear science 2023-04, Vol.70 (4), p.1-1
• Main Authors: Li, Zongru, Elash, Christopher, Jin, Chen, Chen, Li, Wen, Shi-Jie, Fung, Rita, Xing, Jiesi, Shi, Shuting, Yang, Zhi Wu, Bhuva, Bharat L.
• Format: Article
• Language: English
• Subjects: Alpha particles; Alpha rays; Design; Flip-flop (FF); fully-depleted silicon-on-insulator (FDSOI); Hardening; Heavy-Ion; Incidence angle; Inverters; Ions; Irradiation; Layout; radiation hardening by design; Semiconductor devices; Silicon-on-insulator; single event upset; Single event upsets; soft-error rate; SOI (semiconductors); stacked structure; Technology; Transistors; Voltage
• ISSN: 0018-9499; 1558-1578
• DOI: 10.1109/TNS.2023.3257744

Fully depleted silicon-on-insulator (FDSOI) technology nodes offer better single-event performance compared with comparable bulk technologies. However, upsets are still possible at nanoscale feature sizes and additional hardening techniques need to be explored. Single-event upset (SEU) performance of multiple flip-flop designs using the stacked-transistor hardening technique at a 22-nm FDSOI technology node is presented in this paper. Irradiation results show significant reductions in SEU cross-sections for stacked-transistor-based hardened designs compared to a conventional design. Alpha particle exposures showed zero upsets for all D-Flip-Flop (DFF) designs tested. When exposed to heavy-ions, the stacked-transistor DFF design showed a 17X improvement over a conventional DFF design at an LET value of 47 MeV-cm 2 /mg. The stacked-transistor design with the charge-cancelling technique showed upsets when particle LET exceeded 93.8 MeV-cm 2 /mg and at a high angle of incidence. The stacked-transistor design with the interleaving technique showed zero upsets for all test conditions.