A Backside-Illuminated 3.5 μm Pixel With 86% Demodulation Contrast at 1.0 V Voltage Swing for Indirect Time-of-Flight Image Sensors

• Published in: IEEE transactions on electron devices 2023-09, Vol.70 (9), p.4712-4718
• Main Authors: Hu, Congzhen, Zhang, Bing, Xin, Youze, Wang, Chi, Xie, Yiyun, Hu, Pengfei, Ke, Zungui, Geng, Li
• Format: Article
• Language: English
• Subjects: Charge transfer; CMOS image sensors (CISs); Demodulation; Demodulators; Electric fields; Electric potential; Electrostatics; Field effect transistors; full depletion; gate-controlled junction field effect transistor (JFET); Image contrast; indirect time-of-flight (i-ToF); JFET; JFETs; Logic gates; Modulation; photonic demodulator pixel; Photonics; Pixels; Power consumption; Power demand; Quantum efficiency; Semiconductor devices; Sensors
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2023.3298311

This article presents a 3.5 ~\mu \text{m} stacked backside-illuminated (BSI) indirect time-of-flight (i-ToF) pixel fabricated in a 65-nm CMOS image sensors (CIS) process. Transfer gate-induced lateral electric field control of charge transfer is one of the most relied techniques for implementing i-ToF image sensors. However, the transfer gate as modulated gate usually needs a high voltage swing to achieve high demodulation contrast (DC). We introduce a photonic demodulator pixel that utilizes a new lateral electric field modulation technology to achieve a 1.0 V modulation voltage swing while maintaining a high DC of 86% at 100 MHz modulation frequency. The proposed method employs a gate-controlled junction field effect transistor (JFET) to control the drain-induced barrier lowering (DIBL) effect to modulate the lateral electric field. In addition, the photonic demodulator can be also fully depleted with an N-type epitaxy for 22% quantum efficiency (QE) enhancement at 940 nm. This development can greatly lower the power consumption for high-resolution i-ToF sensor applications.