Prototype Design of Global Common Module for ATLAS Experiment's Phase-II Upgrade

• Published in: IEEE transactions on nuclear science 2023-09, Vol.70 (9), p.1-1
• Main Authors: Tang, S., Bonini, F., Begel, M., Benoit, M., Chen, H., Filimonov, V., Lucca, F., Matakias, D., Qian, W., Sankey, D., Xu, H.
• Format: Article
• Language: English
• Subjects: Algorithms; Control systems; Feature extraction; Field programmable gate arrays; Form factors; GCM; Global Trigger; Hardware; Large Hadron Collider; LHC; Luminosity; Mesons; Microprocessors; Microprogramming; Modules; OTHER INSTRUMENTATION; Performance tests; Physics; Power consumption; Prototypes; S phase; Subsystems; Systems design; Telecommunications
• ISSN: 0018-9499; 1558-1578
• DOI: 10.1109/TNS.2023.3302158

A new Global Trigger subsystem will be installed in the Level-0 Trigger as part of HL-LHC Upgrade of ATLAS during the upcoming Long-Shutdown 3. It will feature new and improved trigger hardware and algorithms, and an increased maximum output rate of 1 MHz. The Global Trigger will run offline-like trigger algorithms on full-granularity data, gathered from several sub-detectors and trigger-processing subsystems. A single Global Common Module (GCM) hardware is implemented across the Global Trigger system to be used as Multiplexer Processor, Global Event Processor and CTP Interface (gCTPi). This common hardware platform method will minimize the complexity of the firmware and simplify the system design and long-term maintenance. The GCM prototype is an ATCA front form factor board with two Xilinx Virtex UltraScale+ FPGA VU13P and one ZYNQ UltraScale+ FPGA ZU19EG and seventeen 25.78125 Gb/s FireFly duplex optical modules on it. The total power consumption of this board must be less than 350 W, and the temperature of the optical modules should be less than 70 °C in the worst case. The VU13Ps serve as algorithms processor nodes such as MUX, GEP and gCTPi, and the ZU19EG with Peta Linux OS running on it, is used as Command/Control/Readout Unit to configure and monitor the board and communicate with the ATLAS Detector Control System (DCS). The development of an ATCA blade with three large FPGAs and about 200 optical links running at 25Gb/s is a very challenging task, and the successful test results have demonstrated this GCM prototype as an advancement of state-of-the-art electronics module design in HEP experiments. This paper presents the hardware design considerations, functionalities, and performance test results of this GCM prototype.