Design and Analysis of an Ultralow-Voltage Complementary Fold-Interleaved Multiple-Tail Current Mode Logic

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2023-11, Vol.31 (11), p.1-0
• Main Authors: Malmir, R., Ghaznavi-Ghoushchi, M. B.
• Format: Article
• Language: English
• Subjects: Current mirrors; Current mode logic (CML); Delays; Design analysis; Electric potential; Logic; Logic gates; Metal oxide semiconductors; MOS devices; multiple-folded MOS CML (MFMCML); multiple-tailed CML (MTCML); source coupled logic (SCL); Tail; Transistors; Voltage
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2023.3305915

In this article, we proposed a new design called complementary fold-interleaved multiple-tail current mode logic (CFIMTCML) to implement logical functions with a fan-in higher than 2. This idea is implemented by alternately executing two steps. In the first step, a tail current is divided into multiple currents, but with a shallower depth from the ground to the common-mode point. It is applied on all fully stacked stages. The second step is implemented by alternating nMOS and pMOS differential pairs and utilizing current mirrors in adjacent logic levels. The proposed approach allows a minimum power supply equal to the conventional MCML inverter. Analytical details and design procedures are presented. The method has been validated with post-layout simulations considering 180 nm CMOS technology and supply voltage as low as 0.6 V. In particular, the SOP_X4 is implemented with the conventional SCL, MTCML, multifolded MOS current mode logic (MFMCML), and CFIMTCML. Results show that the proposed logic demonstrates 90%, 20%, and 50% power delay product (PDP) reduction than conventional SCL, MTCML, and MFMCML, respectively. Also, the results of implementation and comparison of other gates, such as the carry generator and 8-bit carry generator demonstrate, at least about 20% reduction of PDP. The delay increase rate at lower voltages for the proposed gates is slower than the counterparts (15 ps at 1.8 V to 124 ps at 0.6 V for the proposed and 27 ps at 1.8 V to 253 ps at 0.6 V for MFMCML). This mitigated degradation is a benefit of the proposed logic for low-noise/low-power applications demanding ultralow voltages.