Gate-stack optimization of a vertically stacked nanosheet FET for digital/analog/RF applications

• Published in: Journal of computational electronics 2022-06, Vol.21 (3), p.608-617
• Main Authors: Tayal, Shubham, Bhattacharya, Sandip, Ajayan, J., Thoutam, Laxman Raju, Muchahary, Deboraj, Jadav, Sunil, Krishan, Bal, Nizamuddin, M.
• Format: Article
• Language: English
• Subjects: Arsenic; CMOS; Dielectrics; Electrical Engineering; Electrons; Engineering; Field effect transistors; Inverters; Investigations; Mathematical and Computational Engineering; Mathematical and Computational Physics; Mechanical Engineering; Nanosheets; Optical and Electronic Materials; Parameters; Semiconductor devices; Silica; Silicon; Silicon dioxide; Simulation; Theoretical; Thickness; Titanium dioxide
• ISSN: 1569-8025; 1572-8137
• DOI: 10.1007/s10825-022-01864-2

Nanosheet field effect transistors (NS-FET) are a most promising candidate for next-generation semiconductor devices for sub-7-nm technology nodes. This work explores a two-channel vertically stacked NS-FET from a digital and analog/RF perspective. The influence of high- κ gate oxide is investigated with respect to the NS-FET-based CMOS inverter and RF/analog parameters of the NS-FET. It is found that the high- κ gate oxide does not change the performance of the NS-FET-based CMOS inverter significantly. Moreover, the proposed NS-FET at L C  = 12 nm exhibits I on , I on / I off , and subthreshold swing (SS) of 646 µA/µm, 1.24 × 10 7 , and 68.8 mV/dec, respectively, for a SiO 2 gate dielectric and 779 µA/µm, 2.5 × 10 7 , and 70 mV/dec, respectively, for a TiO 2 gate dielectric. However, the high- κ gate oxide leads to deterioration in RF/analog parameters of the NS-FET, particularly in weak/moderate regions of operation. To overcome the deterioration caused by the high- κ gate oxide, nanosheet thickness ( T NS ), channel length ( L C ), and spacer dielectric material are optimized. It is revealed that the degradation in RF/analog parameters can be reduced by considering a thicker T NS (10 nm), lower L C (8 nm), and low- κ spacer dielectric (SiO 2 ).