Benchmarking and Optimization of Circular Double Gate Transistor (CDGT) for Sub 10 nm Nodes

• Published in: SILICON 2023-06, Vol.15 (8), p.3549-3558
• Main Authors: Sagar, Kallepelli, Maheshwaram, Satish
• Format: Article
• Language: English
• Subjects: Chemistry; Chemistry and Materials Science; Environmental Chemistry; Field effect transistors; Inorganic Chemistry; Lasers; Materials Science; Nanostructure; Nanowires; Nodes; Optical Devices; Optics; Optimization; Original Paper; Photonics; Polymer Sciences; Radiation; Silicon; Simulation; Transistors
• ISSN: 1876-990X; 1876-9918
• DOI: 10.1007/s12633-022-02282-6

Circular Double Gate Transistors (CDGTs) are one of the alternative promising devices to overcome short-channel effects (SCEs) with improved electrostatic control by two gates. In this paper, the TCAD-based analysis has been carried out on CDGT devices for Low-Power (LP) applications at a 10 nm technology node and extracted DC performance. The proposed device provides better electrical characteristics with an ON current (I ON ) of about ~ 4.52 × 10 –4  A, OFF current (I OFF ) of about ~ 2.62 × 10 –10  A, and an overall I ON /I OFF  of about ~ 1.73 × 10 6 . Further, the proposed CDGT device is benchmarked against advanced novel structures FinFET, Nanowire, and Nanosheet MOSFETs at the same node. It is noticed that our CDGT device outperforms all other devices in terms of device ON current, which is roughly 7 times greater than the next best device (Nanosheet FET). Moreover, we considered the device area to optimize device performance in terms of ON current. The results suggest that when the area is increased to 25% and 50% the total device ON current improves by 19% and 39%, respectively. To predict the suitability of the device at future technology nodes, we have also performed a similar analysis at 7 nm and 5 nm technology nodes. The findings indicate that similar performance is observed and is better suitable for future technology nodes for LP applications with high ON current.