Impact of Gate Length and Doping Variation on the DC and Analog/RF Performance of sub - 3nm Stacked Si Gate-All-Around Nanosheet FET

• Published in: SILICON 2023, Vol.15 (1), p.217-228
• Main Authors: Yadav, Nisha, Jadav, Sunil, Saini, Gaurav
• Format: Article
• Language: English
• Subjects: Chemistry; Chemistry and Materials Science; Design parameters; Doping; Environmental Chemistry; Field effect transistors; Inorganic Chemistry; Lasers; Materials Science; Nanosheets; Nanowires; Optical Devices; Optics; Original Paper; Photonics; Polymer Sciences; Process parameters; Semiconductor devices; Threshold voltage
• ISSN: 1876-990X; 1876-9918
• DOI: 10.1007/s12633-022-01989-w

The nanosheet Field Effect Transistors (FETs) are the promising device architecture for sub - 5 n m technology node as per the International Roadmap for Devices and Systems (IRDS) 2020 and has attracted the semiconductor industry as the key device architecture for upcoming low power to high performance applications. To contribute to the growth of this continuously evolving technology, the impact of key device design parameter namely gate length ( L g ) and process parameters namely source/drain (S/D) doping ( N S D ) and channel doping ( N C H ) on the DC and analog/RF performance of gate-stack based Si gate-all-around (GAA) stacked nanosheet FETs have been explored. Simulation result shows that as we downscale the L g from 30 n m to 10 n m , the short channel effects (SCEs) deteriorates the device performance significantly by reducing the threshold voltage ( V t h ) thereby increasing the OFF-current ( I o f f ) by 4 orders and degrading the sub-threshold swing (SS) and drain induced barrier lowering (DIBL). However, the ON-current ( I o n ), ON-current to OFF-current ratio ( I o n / I o f f ), intrinsic delay and analog/RF performance improves at shorter L g . Higher N S D results in improved driving capability and analog performance of the device. However, I o f f , I o n / I o f f ratio, SS and DIBL degrades with higher N S D . Higher channel doping poses a solution to circumvent the SCEs in aggressively scaled devices, however, it causes scattering thereby reducing the mobility of the carriers. So, the doping should be chosen wisely to get the desired V t h and other performance parameters.