A comparison of embedded and non-embedded FPGA implementations for fractional chaos-based random number generators

• Published in: Journal of ambient intelligence and humanized computing 2023-08, Vol.14 (8), p.11023-11037
• Main Authors: Clemente-Lopez, D., Rangel-Magdaleno, J. J., Munoz-Pacheco, J. M., Morales-Velazquez, L.
• Format: Article
• Language: English
• Subjects: Algorithms; Artificial Intelligence; Chaos theory; Complex systems; Computational Intelligence; Configuration management; Cryptography; Cybersecurity; Design; Digital signal processors; Engineering; Exact solutions; Field programmable gate arrays; Flexibility; Generators; Internet of Things; Microprocessors; Original Research; Power consumption; Power management; Programming languages; Python; Random numbers; Robotics and Automation; System on chip; User Interfaces and Human Computer Interaction
• ISSN: 1868-5137; 1868-5145
• DOI: 10.1007/s12652-022-04382-y

Fractional-order chaotic systems are a hot topic of research due to their applicability in all related fields of science and engineering. For instance, they have been pointed out as a potential solution for security in smart cities and Internet of Things networks through data encryption using random number generators. However, for security applications, one of the main challenges is the physical realization of fractional-order chaotic systems using digital platforms. To overcome this, several works have proposed FPGA technology for implementing complex systems with high computational performance. Nevertheless, the FPGA-based fractional-order chaotic systems implementations require a suitable trade-off between speed performance and hardware cost, especially in embedded approaches that regularly incorporate a system-on-a-chip micro-controller. In this paper, a comparative analysis between the embedded and non-embedded FPGA-based designs for implementing a three-dimensional fractional-order chaotic system and a chaos-based true random number generators is reported. First, we compute a semi-analytical solution of the fractional-order chaotic systems using the Adomian decomposition method, the obtained chaotic time series serves as a random source for the true random number generators. Then, the configuration, resource usage, speed performance, and power consumption of the implementations are tested on a Xilinx Zynq-7000 XC7Z020 system-on-a-chip and an xQuP01v0 FPGA-based processor. The results reveal that while the non-embedded approach showed improved efficiency between cost and performance, the embedded method on the xQuP01v0 FPGA-based processor presented an attractive lower cost-power consumption option against commercial processors.