Enhancement of Performance in TFET by Reducing High-K Dielectric Length and Drain Electrode Thickness

• Published in: SILICON 2020-10, Vol.12 (10), p.2337-2343
• Main Authors: Rani, C. Sheeja Herobin, Bagan, K. Bhoopathy, Nirmal, D., Roach, R. Solomon
• Format: Article
• Language: English
• Subjects: Chemistry; Chemistry and Materials Science; Electrodes; Environmental Chemistry; Field effect transistors; Inorganic Chemistry; Lasers; Materials Science; Optical Devices; Optics; Original Paper; Permittivity; Photonics; Polymer Sciences; Semiconductor devices; Thickness
• ISSN: 1876-990X; 1876-9918
• DOI: 10.1007/s12633-019-00328-w

A Dual Material Double Gate Tunnel Field Effect Transistor (DMDGTFET) with reduced high-K dielectric length (L K  = 15 nm) and drain electrode thickness (6 nm) is proposed and performed a TCAD simulation. The simulation result of proposed device exhibits suppression in gate-to-drain capacitance (C GD ). The (C GD ) is proportional to dielectric constant (ε) of the gate insulator and drain-electrode thickness of device. In the proposed DMDGTFET, the reduction in drain electrode thickness and L K gives a low electron concentration (Q) and low dielectric constant (ε) in channel/drain junction, respectively, which results in suppression of C GD . At V GS  = 2 V, the C GD for the proposed and conventional device are 9 f F, and 7 f F, respectively. In addition, the proposed device exhibit unity current-gain cut-off frequency of 62 GHz, while it is 57 GHz for conventional device. The on-current (I ON ) of the proposed device is also measured as 2 × 10 −5 (A/mm). Thus, the proposed DMDGTFET is potential candidate for fast switching applications without compromising on-current (I ON ).