FPGA implementation novel lightweight MBRISI cipher

The advancement Internet of things has led to an increasing exchange of information. Privacy and security has become a major concern. In this emerging ubiquitous computing world, Lightweight cryptographic algorithms are tailor made to secure the information in low resource devices for the Internet o...

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Bibliographic Details
Published in:Journal of ambient intelligence and humanized computing 2023-09, Vol.14 (9), p.11625-11637
Main Authors: Poojary, Asmita, Kiran Kumar, V. G., Nagesh, H. R.
Format: Article
Language:English
Subjects:
Algorithms
Artificial Intelligence
Computational Intelligence
Correlation coefficients
Cryptography
Design
Efficiency
Encryption
Energy consumption
Engineering
Field programmable gate arrays
Internet of Things
Lightweight
Original Research
Privacy
Robotics and Automation
Software
Ubiquitous computing
User Interfaces and Human Computer Interaction
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Summary:The advancement Internet of things has led to an increasing exchange of information. Privacy and security has become a major concern. In this emerging ubiquitous computing world, Lightweight cryptographic algorithms are tailor made to secure the information in low resource devices for the Internet of Things (IoT) applications. In this paper an area efficient, high performance lightweight cipher, MBRISI cipher is proposed. The cipher is a combination of BRIGHT family of ciphers comprises of Addition-Modulo, Rotation and EX-OR (ARX) operations and the modification of SIMON cipher and also a novel lightweight key generation algorithm is used. The proposed cipher is better than the state of art existing lightweight ciphers and can be extended to support different block sizes and key sizes for the low resource environments like the IoT. The proposed MBRISI cipher encrypts a 32-bit plaintext employing a 64-bit key is implemented and then analyzed. The cipher is implemented in MATLAB tool (for software implementation) and is analyzed for correlation coefficient, entropy and histogram, avalanche criterion and Key-sensitivity. The Verilog code is written and simulated using Xilinx-Vivado tool and synthesized using FPGA’s Artix-7 and Basys-3.
ISSN:1868-5137
1868-5145
DOI:10.1007/s12652-022-03726-y