Current-Voltage Modeling of DRAM Cell Transistor Using Genetic Algorithm and Deep Learning

• Published in: IEEE access 2024, Vol.12, p.23881-23886
• Main Authors: Park, Jun Hui, Kim, Jung Nam, Lee, Seonhaeng, Kim, Gang-Jun, Lee, Namhyun, Baek, Rock-Hyun, Kim, Dae Hwan, Kim, Changhyun, Kang, Myounggon, Kim, Yoon
• Format: Article
• Language: English
• Subjects: BCAT; BSIM-CMG; Buried structures; compact modeling; Current voltage characteristics; Deep learning; Degradation; DRAM cell transistor; Dynamic random access memory; Field effect transistors; genetic algorithm; Genetic algorithms; HCD; I-V modeling; Insulated gate bipolar transistors; Integrated circuit modeling; Integrated circuits; Machine learning; Modelling; Optimization; Random access memory; Semiconductor devices; Sociology; Statistics; Transistors
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2024.3357241

Accurate current-voltage (I-V) modeling based on the Berkeley short-channel insulated-gate field-effect transistor model (BSIM) is pivotal for integrated circuit simulation. However, the current BSIM model does not support a buried-channel-array transistor (BCAT), which is the structure of the state-of-the-art commercial dynamic random access memory (DRAM) cell transistor. In this work, we propose an intelligent I-V modeling technique that combines genetic algorithm (GA) and deep learning (DL). This hybrid technique facilitates both optimization of BSIM parameter and accurate I-V modeling, even for devices not originally supported by BSIM. Additionally, we extended application of the DL to model one of the principal degradation mechanisms of transistor, the hot-carrier degradation (HCD). The successful modeling results of I-V characteristic and device degradation demonstrated that devices not supported by BSIM can be accurately modeled for integrated circuit simulations.