Low power adders using  asynchronous pipelined modified low voltage MCML for signal processing and communication applications

Low power design features have dramatically changed since semiconductors made their move towards deep submicron technologies. In the datapath cells, power dissipation is a major concern since they make up the primitives of higher- level system architectures like microprocessors, Random Access Memory...

Full description

Saved in:
Bibliographic Details
Published in:Analog integrated circuits and signal processing 2024-02, Vol.118 (2), p.343-353
Main Authors: KalavathiDevi, T., Renuka Devi, K. S., Umadevi, S., Sakthivel, P., Ko, Seokbum
Format: Article
Language:English
Subjects:
Adding circuits
Circuit design
Circuits and Systems
Electrical Engineering
Energy dissipation
Engineering
Latches
Low voltage
Metal oxide semiconductors
Microprocessors
Power consumption
Power management
Random access memory
Signal generation
Signal processing
Signal,Image and Speech Processing
Citations: Items that this one cites
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Low power design features have dramatically changed since semiconductors made their move towards deep submicron technologies. In the datapath cells, power dissipation is a major concern since they make up the primitives of higher- level system architectures like microprocessors, Random Access Memory (RAM) cells and mobile architectures. By combining low voltage MOS Current Mode Logic (MCML) with two phase bundled data protocol, the manuscript describes a practical method for designing combinational circuits. Asynchronous pipeline circuits can accomplish higher throughput, reduced latency, and consume less power than synchronous pipeline circuits without experiencing clock skew problems. Muller C-elements are used to produce control signals in the handshaking path and D latches areemployed to ensure that the control signal generation proceeds in two phases. The proposed concept is implemented in 1-bit full adder and 4bit Carry Look Ahead (CLA) adder and simulated inT-SPICE using TSMC 45 nm technology library. In comparison to conventional MCML-based 4-bit CLA adder, asynchronous pipelined low voltage MCML implementation achieves 24% reduced power consumption, 19% less computation time, and 39% less Power Delay Product (PDP).
ISSN:0925-1030
1573-1979
DOI:10.1007/s10470-023-02241-0