Network-on-Chip Trust Validation Using Security Assertions

• Published in: Journal of hardware and systems security 2022-12, Vol.6 (3-4), p.79-94
• Main Authors: Jayasena, Aruna, Kumar, Binod, Charles, Subodha, Witharana, Hasini, Mishra, Prabhat
• Format: Article
• Language: English
• Subjects: Algorithms; Automation; Circuits and Systems; Communication; Computer Hardware; Design; Engineering; Information Systems Applications (incl.Internet); Intellectual property; Routers; Security; Silicon; System on chip; Systems and Data Security
• ISSN: 2509-3428; 2509-3436
• DOI: 10.1007/s41635-022-00129-5

Recent technological advancements enabled integration of a wide variety of Intellectual Property (IP) cores in a single chip, popularly known as System-on-a-Chip (SoC). Network-on-Chip (NoC) is a scalable solution that enables communication between a large number of IP cores in modern SoC designs. A typical SoC design methodology relies on third-party IPs to reduce cost and meet time-to-market constraints, leading to serious security concerns. NoC becomes an ideal target for attackers due to its distributed nature across the chip as well as its inherent ability in monitoring communications between the individual IP cores. This paper presents a comprehensive NoC trust validation framework using security assertions. It makes three important contributions. (1) We define a set of security vulnerabilities for NoC architectures, and propose security assertions to monitor these pre-silicon vulnerabilities. (2) In order to ensure that the generated assertions are valid, we utilize efficient test generation techniques to activate these security assertions. (3) We develop on-chip triggers based on synthesized security assertions as well as efficient security-aware signal selection techniques for effective post-silicon debug. Experimental results show that our proposed framework is scalable and effective in capturing security vulnerabilities as well as functional bugs with minor hardware overhead.