Simulation of capacitorless DRAM based on polycrystalline silicon with a vertical underlap structure and a separated channel layer

• Published in: Japanese Journal of Applied Physics 2024-03, Vol.63 (3), p.3
• Main Authors: Bae, Seung Ji, Lee, Sang Ho, Park, Jin, Kang, Ga Eon, Heo, Jun Hyeok, Jeon, So Ra, Kim, Min Seok, Hong, Jeong Woo, Jang, Jaewon, Bae, Jin-Hyuk, Lee, Sin-Hyung, Kang, In Man
• Format: Article
• Language: English
• Subjects: 1T-DRAM; Dynamic random access memory; Grain boundaries; grain boundary; polycrystalline silicon; Polycrystals; Polysilicon; retention time; sensing margin; Silicon; Storage; Thickness; underlap; vertical underlap
• ISSN: 0021-4922; 1347-4065
• DOI: 10.35848/1347-4065/ad2bbd

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on polycrystalline silicon (poly-Si) with a vertical underlap structure and a separated channel layer was designed and analyzed. The memory performance was improved by the vertical underlap structure and the region separated into channel and storage layers. The vertical underlap structure suppressed the recombination rate by storing the holes in the isolated body and could be more easily fabricated than a conventional underlap structure. The thicknesses of the vertical underlap structure and storage region were optimized to enhance the memory performance. When the grain boundary (GB) is centrally located, the proposed 1T-DRAM demonstrates a retention time and sensing margin of 3.618 s and 29.93 μ A μ m −1 , respectively. Even when the GB is in the worst position at T = 358 K, the memory still shows a retention time of 1.991 s and a sensing margin of 4.51 μ A μ m −1 .