PROBE3.0: A Systematic Framework for Design-Technology Pathfinding With Improved Design Enablement

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 2024-04, Vol.43 (4), p.1218-1231
• Main Authors: Choi, Suhyeong, Jung, Jinwook, Kahng, Andrew B., Kim, Minsoo, Park, Chul-Hong, Pramanik, Bodhisatta, Yoon, Dooseok
• Format: Article
• Language: English
• Subjects: Business process re-engineering; Clustering; Configuration management; Design improvements; Design parameters; Design standards; Design-technology co-optimization (DTCO); FinFETs; Integrated circuit interconnections; Layout; Libraries; Logic gates; Machine learning; Performance evaluation; physical design; place-and-route (P&R); routability; standard cell; Systematics; technology pathfinding; VLSI CAD
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2023.3334591

We propose a systematic framework to conduct design-technology pathfinding for power, performance, area, and cost (PPAC) in advanced nodes. Our goal is to provide a configurable, scalable generation of process design kit (PDK) and standard-cell library, spanning key scaling boosters (backside PDN and buried power rail), to explore PPAC across given technology and design parameters. We build on Cheng et al. (2022), which addressed only area and cost (AC), to include power and performance (PP) evaluations through automated generation of full design enablements. We also improve the use of artificial designs in the PPAC assessment of technology and design configurations. We generate more realistic artificial designs by applying a machine learning-based parameter tuning flow to Kim et al. (2022). We further employ clustering-based cell width-regularized placements at the core of routability assessment, enabling more realistic placement utilization and improved experimental efficiency. We evaluate PPAC across scaling boosters and artificial designs in a predictive technology node.