Neural Architecture Search with In‐Memory Multiply–Accumulate and In‐Memory Rank Based on Coating Layer Optimized C‐Doped Ge2Sb2Te5 Phase Change Memory

• Published in: Advanced functional materials 2024-04, Vol.34 (15), p.n/a
• Main Authors: Yan, Longhao, Wu, Qingyu, Li, Xi, Xie, Chenchen, Zhou, Xilin, Li, Yuqi, Shi, Daijing, Yu, Lianfeng, Zhang, Teng, Tao, Yaoyu, Yan, Bonan, Zhong, Min, Song, Zhitang, Yang, Yuchao, Huang, Ru
• Format: Article
• Language: English
• Subjects: Chips (memory devices); Cognitive tasks; Computation; Computer architecture; Computer memory; Graphics processing units; in‐memory computing; in‐memory rank; Machine learning; neural architecture search; Neural networks; operators; phase change memory
• ISSN: 1616-301X; 1616-3028
• DOI: 10.1002/adfm.202300458

Neural architecture search (NAS), as a subfield of automated machine learning, can design neural network models with better performance than manual design. However, the energy and time consumptions of conventional software‐based NAS are huge, hindering its development and applications. Herein, 4 Mb phase change memory (PCM) chips are first fabricated that enable two key in‐memory computing operations—in‐memory multiply‐accumulate (MAC) and in‐memory rank for efficient NAS. The impacts of the coating layer material are systematically analyzed for the blade‐type heating electrode on the device uniformity and in turn NAS performance. The random weights in the searched network architecture can be fine‐tuned in the last stage. With 512 × 512 arrays based on 40 nm CMOS process, the PCM‐based NAS has achieved 25–53× smaller model size and better performance than manually designed networks and improved the energy and time efficiency by 4779× and 123×, respectively, compared with NAS running on graphic processing unit (GPU). This work can expand the hardware accelerated in‐memory operators, and significantly extend the applications of in‐memory computing enabled by nonvolatile memory in advanced machine learning tasks. Herein, 4 Mb phase change memory chips are first fabricated that enable two key in‐memory computing operations—in‐memory multiply accumulate (MAC) and in‐memory rank for efficient NAS. With 512 × 512 arrays the PCM‐based NAS has achieved 25–53× smaller model size and better performance than manually designed networks, and improved the energy and time efficiency by 4779× and 123×, respectively, compared with GPU.