Design Considerations and Their Optimization for a Two-Level GaN-Based Current Source Inverter

This article presents an application of gallium nitride (GaN) devices for the development of a three-phase two-level current source inverter (2L-CSI). Its high-frequency operation at extremely low temperatures can offer higher power efficiencies and densities because of the improved performance of G...

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Bibliographic Details
Published in:IEEE journal of emerging and selected topics in power electronics 2024-06, Vol.12 (3), p.3173-3187
Main Authors: Ul Hassan, Mustafeez, Wu, Yuxuan, Imran Emon, Asif, Yuan, Zhao, Luo, Fang
Format: Article
Language:English
Subjects:
Current source inverter (CSI)
Current sources
Design optimization
Devices
Electric potential
Gallium nitrides
Inductance
Inverters
Layout
Low temperature
modified double pulse test (DPT)
Optimization
paralleled gallium nitride (GaN) devices
Performance evaluation
power loop inductance
Power rating
Silicon carbide
Switches
Voltage
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Summary:This article presents an application of gallium nitride (GaN) devices for the development of a three-phase two-level current source inverter (2L-CSI). Its high-frequency operation at extremely low temperatures can offer higher power efficiencies and densities because of the improved performance of GaN devices and inductive dc link storage elements. However, higher power rating CSI with paralleled GaN devices together with symmetrical and optimized power loop, and overall converter structure. An imbalanced and larger power loop can result in severe device overshoots, imbalanced switching loss distribution, and imbalanced ripple across output voltage. However, less effort has been spent to understand the intricacies of a CSI. This article presents a comprehensive study of all the layout-induced challenges in a CSI using parallel-connected GaN devices by introducing multiple objectives. Furthermore, the impact of the passive phase (PP) has also been recognized leading to a modified double pulse test (DPT). This article develops two different converter structures with state-of-the-art symmetrical power loop inductance of 3.98 nH and parasitics capacitance of 6.22 pF, and therefore improved output voltage quality. Numerous hardware results together with continuous operation of the converter were presented till 100 V with a peak value of measured efficiencies around 97.63% to prove the process of optimization.
ISSN:2168-6777
2168-6785
DOI:10.1109/JESTPE.2024.3391005