Real-time Digital RF Emulation -- I: The Direct Path Computational Model

• Published in: arXiv.org 2024-06
• Main Authors: Coleman DeLude, Driscoll, Joe, Mukherjee, Mandovi, Rahman, Nael, Kamal, Uday, Mao, Xiangyu, Khan, Sharjeel, Sivaraman, Hariharan, Huang, Eric, McHarg, Jeffrey, Swaminathan, Madhavan, Pande, Santosh, Mukhopadhyay, Saibal, Romberg, Justin
• Format: Article
• Language: English
• Subjects: Delay lines; Emulators; Hardware
• ISSN: 2331-8422

In this paper we consider the problem of developing a computational model for emulating an RF channel. The motivation for this is that an accurate and scalable emulator has the potential to minimize the need for field testing, which is expensive, slow, and difficult to replicate. Traditionally, emulators are built using a tapped delay line model where long filters modeling the physical interactions of objects are implemented directly. For an emulation scenario consisting of \(M\) objects all interacting with one another, the tapped delay line model's computational requirements scale as \(O(M^3)\) per sample: there are \(O(M^2)\) channels, each with \(O(M)\) complexity. In this paper, we develop a new ``direct path" model that, while remaining physically faithful, allows us to carefully factor the emulator operations, resulting in an \(O(M^2)\) per sample scaling of the computational requirements. The impact of this is drastic, a \(200\) object scenario sees about a \(100\times\) reduction in the number of per sample computations. Furthermore, the direct path model gives us a natural way to distribute the computations for an emulation: each object is mapped to a computational node, and these nodes are networked in a fully connected communication graph. Alongside a discussion of the model and the physical phenomena it emulates, we show how to efficiently parameterize antenna responses and scattering profiles within this direct path framework. To verify the model and demonstrate its viability in hardware, we provide several numerical experiments produced using a cycle level C++ simulator of a hardware implementation of the model.