CMOS Logic and Capacitorless DRAM by Stacked Oxide Semiconductor and Poly-Si Transistors for Monolithic 3-D Integration

In this work, we demonstrate capacitorless dynamic random access memory (DRAM) and complementary metal-oxide-semiconductor (CMOS) logic circuits by vertically stacked ZnO transistors and low-temperature polycrystalline silicon (LTPS) transistors on the same chip. High-performance ZnO transistors are...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2024-08, Vol.71 (8), p.4664-4669
Main Authors: Wang, Ziheng, Zheng, Liankai, Lin, Zhiyu, Zhao, Jinxiu, Tang, Wei, Feng, Linrun, Liu, Zhe, Li, Xuefei, Guo, Xiaojun, Si, Mengwei
Format: Article
Language:English
Subjects:
Atomic layer epitaxy
Capacitance
Capacitorless dynamic random access memory (DRAM)
CMOS
Dynamic random access memory
Field effect transistors
II-VI semiconductor materials
Iron
Logic circuits
Logic gates
Low temperature
Metal oxides
monolithic 3-D (M3D) integration
oxide semiconductor
Polysilicon
Random access memory
Silicon
Transistors
Voltage gain
Zinc oxide
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Summary:In this work, we demonstrate capacitorless dynamic random access memory (DRAM) and complementary metal-oxide-semiconductor (CMOS) logic circuits by vertically stacked ZnO transistors and low-temperature polycrystalline silicon (LTPS) transistors on the same chip. High-performance ZnO transistors are achieved by atomic layer deposition, exhibiting a field-effect mobility ( \mu _{\text {FE}}\text {)} of 35.2 cm2/V \cdot s, subthreshold slope (SS) down to 71 mV/dec, and low off-state current (I _{\text {OFF}}\text {)} \lt 2\times 10^{-{19}} A/ \mu m. Such ZnO transistors are used as write transistors in the capacitorless two transistor (2T0C) DRAM cell and as n-FETs in the CMOS logic gates, achieving long retention time with memory window (MW) (I _{\text {state {1}}} /I _{\text {state {0}}}\text {)} \gt 10^{{4}} after 10^{{4}} s in DRAM (at a storage capacitance of 130 fF) and high inverter voltage gain of 181 V/V at VDD of 4.5 V in CMOS logic. Besides, a novel 2T0C DRAM with LTPS p-FET as read transistors is demonstrated, showing enhanced storage node voltage (V _{\text {SN}}\text {)} enabled by coupling capacitance, providing a promising approach to improve retention and reduce operating voltage for 2T0C DRAM.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2024.3418768