Data-Efficient Prediction of Minimum Operating Voltage via Inter- and Intra-Wafer Variation Alignment

Predicting the minimum operating voltage (\(V_{min}\)) of chips stands as a crucial technique in enhancing the speed and reliability of manufacturing testing flow. However, existing \(V_{min}\) prediction methods often overlook various sources of variations in both training and deployment phases. No...

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Bibliographic Details
Published in:arXiv.org 2024-08
Main Authors: Yin, Yuxuan, Chen, Rebecca, Chen, He, Li, Peng
Format: Article
Language:English
Subjects:
Alignment
Electric potential
Predictions
Reliability
Voltage
Online Access:Get full text
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Summary:Predicting the minimum operating voltage (\(V_{min}\)) of chips stands as a crucial technique in enhancing the speed and reliability of manufacturing testing flow. However, existing \(V_{min}\) prediction methods often overlook various sources of variations in both training and deployment phases. Notably, the neglect of wafer zone-to-zone (intra-wafer) variations and wafer-to-wafer (inter-wafer) variations, compounded by process variations, diminishes the accuracy, data efficiency, and reliability of \(V_{min}\) predictors. To address this gap, we introduce a novel data-efficient \(V_{min}\) prediction flow, termed restricted bias alignment (RBA), which incorporates a novel variation alignment technique. Our approach concurrently estimates inter- and intra-wafer variations. Furthermore, we propose utilizing class probe data to model inter-wafer variations for the first time. We empirically demonstrate RBA's effectiveness and data efficiency on an industrial 16nm automotive chip dataset.
ISSN:2331-8422