Analog Spiking Neuron in CMOS 28 nm Towards Large-Scale Neuromorphic Processors

• Published in: arXiv.org 2024-08
• Main Authors: Besrour, Marwan, Lavoie, Jacob, Omrani, Takwa, Martin-Hardy, Gabriel, Esmaeil Ranjbar Koleibi, Menard, Jeremy, Koua, Konin, Marcoux, Philippe, Boukadoum, Mounir, Fontaine, Rejean
• Format: Article
• Language: English
• Subjects: Algorithms; Back propagation networks; CMOS; Deep learning; Energy efficiency; Energy limitation; Machine learning; Memory devices; Neural networks; Platforms; Portable equipment; Power management; Spiking; System on chip
• ISSN: 2331-8422

The computational complexity of deep learning algorithms has given rise to significant speed and memory challenges for the execution hardware. In energy-limited portable devices, highly efficient processing platforms are indispensable for reproducing the prowess afforded by much bulkier processing platforms. In this work, we present a low-power Leaky Integrate-and-Fire (LIF) neuron design fabricated in TSMC's 28 nm CMOS technology as proof of concept to build an energy-efficient mixed-signal Neuromorphic System-on-Chip (NeuroSoC). The fabricated neuron consumes 1.61 fJ/spike and occupies an active area of 34 \(\mu m^{2}\), leading to a maximum spiking frequency of 300 kHz at 250 mV power supply. These performances are used in a software model to emulate the dynamics of a Spiking Neural Network (SNN). Employing supervised backpropagation and a surrogate gradient technique, the resulting accuracy on the MNIST dataset, using 4-bit post-training quantization stands at 82.5\%. The approach underscores the potential of such ASIC implementation of quantized SNNs to deliver high-performance, energy-efficient solutions to various embedded machine-learning applications.