Design of Yolov4-Tiny convolutional neural network hardware accelerator based on FPGA

This article designs a Yolov4 Tiny convolutional neural network hardware accelerator based on FPGA. A four-stage pipeline convolutional array structure has been proposed. In the design, the NC4HW4 parameter rearrangement and Im2col dimensionality reduction algorithm are used as the core to maximize...

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Bibliographic Details
Published in:Journal of physics. Conference series 2024-09, Vol.2849 (1), p.12005
Main Authors: Du, Wenhe, Chen, Shuoyu, Wang, Lei, Chai, Ruili
Format: Article
Language:English
Subjects:
Algorithms
Artificial neural networks
Computation
Field programmable gate arrays
Hardware
Object recognition
Pipelining (computers)
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Summary:This article designs a Yolov4 Tiny convolutional neural network hardware accelerator based on FPGA. A four-stage pipeline convolutional array structure has been proposed. In the design, the NC4HW4 parameter rearrangement and Im2col dimensionality reduction algorithm are used as the core to maximize the parallelism of matrix operations under limited resources. Secondly, a PE convolutional computing unit structure was designed, and a resource-efficient and highly reliable convolutional computing module was implemented by combining INT8 DSP resource reuse technology. Finally, the accelerator will be deployed on Xilinx’s Zynq7030 development board. The experimental results show that at a clock frequency of 130 MHz, the power consumption of the hardware accelerator is only 2.723 W, and the performance is 59.54 Gbps. Compared with related research, it has improved more than 2.1 times. This accelerator can complete hardware-accelerated computing tasks in object detection with high energy efficiency.
ISSN:1742-6588
1742-6596
DOI:10.1088/1742-6596/2849/1/012005