Design of domino logic circuits using geometric programming

• Main Authors: Varghese, Avino Maria, George, Retty, Thomas, Aby, Resma, K. R.
• Format: Conference Proceeding
• Language: English
• Subjects: Circuits; Cochlear implants; Delay; Logic circuits; Mathematical programming; Maximum power; Microprocessors; Modelling; Optimization techniques; Surgical implants; Transistor logic; Transistors
• ISSN: 0094-243X; 1551-7616
• DOI: 10.1063/5.0227553

With the advancement in the field of microprocessors, and FPGAs, the need for optimized devices increased significantly. Two significant issues with CMOS VLSI circuits in deep-submicron technology are leakage power and propagation delay. Development in the medical field, such as pacemakers, cochlear implants, etc., deepened this requirement. This paper proposes an optimization technique: Geometric Programming (GP), which is illustrated using Foot Driven Stack Transistor Logic (FDSTL), a power-saving domino circuit. Among the different modeling methods available within GP, this work focuses on the sizing of transistors and thereby reducing power without affecting delay and area. This method employs the Elmore delay modeling to obtain generalized posynomials. The implementation of the primal-dual interior point method for GP is done in GGPLAB, a Matlab-based toolbox for GP. The optimized width obtained through ggplab is subsequently simulated in 180nm PTM technology, at 1.8v, using Tanner EDA. The parameters selected for the comparison of the proposed domino logic circuit with existing circuits are power and delay. The simulation results show that with the use of GP, the maximum power is reduced by approximately 60% compared to the original FDSTL circuit.