Unipolar p-type monolayer WSe2 field-effect transistors with high current density and low contact resistance enabled by van der Waals contacts

• Published in: Nano research 2024-11, Vol.17 (11), p.10162-10169
• Main Authors: Li, Miaomiao, Zhang, Xinyu, Zhang, Zimei, Peng, Gang, Zhu, Zhihong, Li, Jia, Qin, Shiqiao, Zhu, Mengjian
• Format: Article
• Language: English
• Subjects: Atomic/Molecular Structure and Spectra; Biomedicine; Biotechnology; Chemical vapor deposition; Chemistry and Materials Science; Communication; Condensed Matter Physics; Contact resistance; Current density; Electric contacts; Electrical junctions; Fabrication; Fermi level; Field effect transistors; Hole mobility; Integrated circuits; Logic circuits; Low dimensional semiconductors; Materials Science; Metals; Monolayers; Nanotechnology; P-type semiconductors; Palladium; Pinning; Room temperature; Scale (corrosion); Semiconductor devices; Semiconductor junctions; Semiconductors; Transistors
• ISSN: 1998-0124; 1998-0000
• DOI: 10.1007/s12274-024-6942-5

High-performance field-effect transistors (FETs) based on atomically thin two-dimensional (2D) semiconductors have demonstrated great promise in post-Moore integrated circuits. However, unipolar p-type 2D semiconductor transistors yet remain challenging and suffer from low saturation current density (less than 10 µA·µm −1 ) and high contact resistance (larger than 100 kΩ·µm), mainly limited by the Schottky barrier induced by the mismatch of the work-functions and the Fermi level pinning at the metal contact interfaces. Here, we overcome these two obstacles through van der Waals (vdW) integration of high work-function metal palladium (Pd) as the contacts onto monolayer WSe 2 grown by chemical vapor deposition (CVD) method. We demonstrate unipolar p-type monolayer WSe 2 FETs with superior device performance: room temperature on-state current density exceeding 100 µA·µm −1 , contact resistance of 12 kΩ·µm, on/off ratio over 10 7 , and field-effect hole mobility of ~ 103 cm 2 ·V −1 ·s −1 . Electrical transport measurements reveal that the Fermi level pinning effect is completely effectively eliminated in monolayer WSe 2 with vdW Pd contacts, leading to a Schottky barrier-free Ohmic contact at the metal-semiconductor junctions. Combining the advantages of large-scale vdW contact strategy and CVD growth, our results pave the way for wafer-scale fabrication of complementary-metal-oxide-semiconductor (CMOS) logic circuits based on atomically thin 2D semiconductors.