ReD: A Reliable and Deadlock-Free Routing for 2.5-D Chiplet-Based Interposer Networks

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 2024-12, Vol.43 (12), p.4599-4612
• Main Authors: Taheri, Ebadollah, Pasricha, Sudeep, Nikdast, Mahdi
• Format: Article
• Language: English
• Subjects: Algorithms; Chiplet systems; Circuit faults; Congestion; deadlock freedom; Fault tolerance; Fault tolerant systems; Faults; Freeports; Modular systems; Network latency; networks on chip (NoCs); Routing; Routing (telecommunications); System on chip; System recovery; Three-dimensional displays; Virtual networks
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2024.3399660

2.5-D integration offers a cost-effective and reliable solution for implementing large-scale modular systems. A 2.5-D chiplet system can be designed by connecting smaller chiplets through an interposer, where the chiplets may have heterogeneous architectures. In addition to the intrachiplet network (e.g., a network-on-chip on the chiplet), a network is used on the interposer to enable efficient and scalable communication among different chiplets. However, this global network, which consists of intrachiplet and interchiplet networks, is susceptible to deadlock, despite using deadlock-free networks on the chiplets and interposer. Moreover, 2.5-D networks are not only vulnerable to horizontal link (HL) faults but also to those in the vertical links (VLs) connecting the chiplets to the interposer. In addition, such faults cannot be effectively addressed by existing fault-tolerant routing techniques designed for 2-D and 3-D networks on chip. To overcome these challenges, this article introduces a novel reliable and deadlock-free routing algorithm, called ReD, for fault-tolerant communication in 2.5-D chiplet systems. ReD leverages a virtual-network-based approach to guarantee deadlock freedom while tolerating VL and HL faults. Besides VL faults, due to the difference in VL technology (i.e., microbump technology), the number of VLs connecting a chiplet to the interposer is limited, making VLs a source of congestion. ReD enhances VL selection in such scenarios to tolerate VL faults and improve network congestion by balancing VL utilization. Compared to the state-of-the-art routing algorithms, simulation results obtained by simulating chiplet systems under HL and VL faults demonstrate that ReD significantly improves the network reachability by up to 75% and reduces the network latency by up to 40%, while incurring less than 2% area overhead.