HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection

Hardware intellectual-property (IP) cores have emerged as an integral part of modern system-on-chip (SoC) designs. However, IP vendors are facing major challenges to protect hardware IPs from IP piracy. This paper proposes a novel design methodology for hardware IP protection using netlist-level obf...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 2009-10, Vol.28 (10), p.1493-1502
Main Authors: Chakraborty, R.S., Bhunia, S.
Format: Article
Language:English
Subjects:
Chip scale packaging
Circuits
Computer information security
Costs
Delay
Design engineering
Design for security
Design methodology
Hardness
Hardware
hardware authentication
hardware obfuscation
intellectual-property (IP) piracy
IP (Internet Protocol)
IP protection
Manufacturing
Methodology
Power system security
Protection
Reverse engineering
System-on-a-chip
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Summary:Hardware intellectual-property (IP) cores have emerged as an integral part of modern system-on-chip (SoC) designs. However, IP vendors are facing major challenges to protect hardware IPs from IP piracy. This paper proposes a novel design methodology for hardware IP protection using netlist-level obfuscation. The proposed methodology can be integrated in the SoC design and manufacturing flow to simultaneously obfuscate and authenticate the design. Simulation results for a set of ISCAS-89 benchmark circuits and the advanced-encryption-standard IP core show that high levels of security can be achieved at less than 5% area and power overhead under delay constraint.
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2009.2028166