Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

• Published in: IEEE transactions on advanced packaging 2006-11, Vol.29 (4), p.674-682
• Main Authors: Chong, D.Y.R., Lim, B.K., Rebibis, K.J., Pan, S.J., Sivalingam, K., Kapoor, R., Sun, A.Y.S., Tan, H.B.
• Format: Article
• Language: English
• Subjects: Applied sciences; Arrays; BGA; Chips; Counting; Design. Technologies. Operation analysis. Testing; Electronics; Electronics packaging; Encapsulation; Exact sciences and technology; Exposure; Fatigue; Finite element methods; Flip chip; Flip chip ball grid array (BGA); high performance; high pin count; Integrated circuits; Packages; Printed circuit boards; Semiconductor device packaging; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; solder joints reliability; Soldering; Solders; Studies; Substrates; superior heat dissipation; Temperature; thermal dissipation; Thermal loading
• ISSN: 1521-3323; 1557-9980
• DOI: 10.1109/TADVP.2006.884776

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported