The influence of processor architecture on the design and the results of WCET tools

The architecture of tools for the determination of worst case execution times (WCETs) as well as the precision of the results of WCET analyses strongly depend on the architecture of the employed processor. The cache replacement strategy influences the results of cache behavior prediction; out-of-ord...

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Bibliographic Details
Published in:Proceedings of the IEEE 2003-07, Vol.91 (7), p.1038-1054
Main Authors: Heckmann, R., Langenbach, M., Thesing, S., Wilhelm, R.
Format: Article
Language:English
Subjects:
Architecture
Bridges
Computer architecture
Demand analysis
Design engineering
Marketing
Microprocessors
Modular design
Out of order
Performance analysis
Pipelines
Power system modeling
Processor scheduling
Real time systems
Strategy
Timing
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Summary:The architecture of tools for the determination of worst case execution times (WCETs) as well as the precision of the results of WCET analyses strongly depend on the architecture of the employed processor. The cache replacement strategy influences the results of cache behavior prediction; out-of-order execution and control speculation introduce interferences between processor components, e.g., caches, pipelines, and branch prediction units. These interferences forbid modular designs of WCET tools, which would execute the subtasks of WCET analysis consecutively. Instead, complex integrated designs are needed, resulting in high demand for memory space and analysis time. We have implemented WCET tools for a series of increasingly complex processors: SuperSPARC, Motorola ColdFire 5307, and Motorola PowerPC 755. In this paper, we describe the designs of these tools, report our results and the lessons learned, and give some advice as to the predictability of processor architectures.
ISSN:0018-9219
1558-2256
DOI:10.1109/JPROC.2003.814618