Bit-Cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching

• Published in: IEEE transactions on nanotechnology 2012-01, Vol.11 (1), p.172-181
• Main Authors: Xuanyao Fong, Choday, S. H., Roy, K.
• Format: Article
• Language: English
• Subjects: Applied sciences; Circuit optimization; Computer simulation; Current density; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Failure; Integrated circuits; Integrated circuits by function (including memories and processors); magnetic memories; magnetic tunnel junctions (MTJ); Magnetic tunneling; Magnetization; Magnetoelectric, magnetostrictive, magnetoacoustic, magnetooptic and magnetothermal devices. Spintronics; Mathematical model; Mathematical models; memory architectures; Nanotechnology; Optimization; Optimization techniques; Resistance; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; spin-transfer torque MRAM (STT-MRAM) bit-cells; Studies; Switches; Torque; Transistors; Tunnel junctions
• ISSN: 1536-125X; 1941-0085
• DOI: 10.1109/TNANO.2011.2169456

Spin-transfer torque magnetic random access memories (STT-MRAM), using magnetic tunnel junctions (MTJ), is a resistive memory technology that has spurred significant research interest due to its potential for on-chip, high-density, high-speed, low-power, and non-volatile memory. However, due to conflicting read and write requirements, there is a need to develop optimization techniques for designing STT-MRAM bit-cells to minimize read and write failures. We propose an optimization technique that minimizes read and write failures by proper selection of bit-cell configuration and by proper access transistor sizing. A mixed-mode simulation framework was developed to evaluate the effectiveness of our optimization technique. Our simulation framework captures the transport physics in the MTJ using Non-Equilibrium Green's Function method and self-consistently solves the MTJ magnetization dynamics using Landau-Lifshitz-Gilbert equation augmented with the full Slonczewski spin-torque term. The electrical parameters of the MTJ are then encapsulated in a Verilog-A model and used in HSPICE to perform bit-cell level optimization. The optimization technique is applied to STT-MRAM bit-cells designed using 45 nm bulk and 45 nm silicon-on-insulator CMOS technologies. Finally, predictions are made for optimized STT-MRAM bit-cells designed in 16 nm predictive technology.