Criticality guided energy aware speculation for speculative multithreaded processors

• Published in: Parallel computing 2012-06, Vol.38 (6-7), p.329-341
• Main Authors: Nagpal, Rahul, Bhowmik, Anasua
• Format: Article
• Language: English
• Subjects: Architecture; Computation; Delay; Dynamics; Energy consumption; Energy optimization; Execution modeling; Instruction criticality; Loads (forces); Performance enhancement; Prediction; Processors; Speculation control; Speculative multithreading
• ISSN: 0167-8191; 1872-7336
• DOI: 10.1016/j.parco.2012.03.002

► SpMT philosophy uses aggressive speculative execution for improved performance. ► Speculative execution improves performance but increases energy on mis-speculation. ► We presented model of SpMT execution for determining dynamic instruction criticality. ► Proposed criticality based load delaying and thread-prediction schemes save energy. ► Detail experimental evaluation shows significant energy savings. Unending quest for performance improvement coupled with the advancements in integrated circuit technology have led to the development of new architectural paradigm. Speculative multithreaded architecture (SpMT) philosophy relies on aggressive speculative execution for improved performance. However, aggressive speculative execution comes with a mixed flavor of improving performance, when successful, and adversely affecting the energy consumption (and performance) because of useless computation in the event of mis-speculation. Dynamic instruction criticality information can be usefully applied to control and guide such an aggressive speculative execution. In this paper, we present a model of micro-execution for SpMT architecture that we have developed to determine the dynamic instruction criticality. We have also developed two novel techniques utilizing the criticality information namely delaying the non-critical loads and the criticality based thread-prediction for reducing useless computations and energy consumption. Experimental results showing break-up of critical instructions and effectiveness of proposed techniques in reducing energy consumption are presented in the context of multiscalar processor that implements SpMT architecture. Our experiments show 17.7% and 11.6% reduction in dynamic energy for criticality based thread prediction and criticality based delayed load scheme respectively while the improvement in dynamic energy delay product is 13.9% and 5.5%, respectively.