Misalignment induced shear deformation in 3D chip stacking: A parametric numerical assessment

The misalignment effect in three dimensional (3D) chip packages is studied numerically using the finite element method (FEM). The model features a through-silicon-via (TSV)/micro-bump bonding structure connecting two adjacent silicon (Si) chips, with and without surrounding underfill. Misalignment i...

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Bibliographic Details
Published in:Microelectronics and reliability 2013-01, Vol.53 (1), p.79-89
Main Authors: Shen, Y.-L., Johnson, R.W.
Format: Article
Language:English
Subjects:
Chips
Finite element method
Intermetallics
Mathematical models
Misalignment
Shear deformation
Solders
Three dimensional
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Summary:The misalignment effect in three dimensional (3D) chip packages is studied numerically using the finite element method (FEM). The model features a through-silicon-via (TSV)/micro-bump bonding structure connecting two adjacent silicon (Si) chips, with and without surrounding underfill. Misalignment is implemented through a prescribed shear deformation, and we seek to parametrically explore the trend of stress and deformation fields as affected by the geometry and material. Different solder thicknesses in the micro-bump, as well as a special case where the entire solder region is transformed into the intermetallic compound, are considered in this study. The effects of shear deformation are also compared with those due to thermal expansion mismatch. A thinner solder region in the micro-bump is found to have a higher propensity of damage initiation. The existence of underfill enhances the resistance to overall shear deformation, although with a much greater buildup of local stresses. With an intermetallic layer in place of the soft solder alloy in the micro-bump, the overall shear strength of the structure increases but with a concomitant increase in the risk of local brittle failure.
ISSN:0026-2714
1872-941X
DOI:10.1016/j.microrel.2012.04.018